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1 for more information www.linear.com/ltc2311-16 typical application features description 16-bit, 5msps differential input adc with wide input common mode range the lt c ? 2311- 16 is a low noise, high speed 16- bit successive approximation register (sar) adc with differential inputs and wide input common mode range. operating from a single 3.3v or 5v supply, the ltc2311- 16 has an 8v p-p differential input range, making it ideal for applications which require a wide dynamic range with high common mode rejection. the ltc2311-16 achieves 3lsb inl typical, no missing codes at 16 bits and 81db snr typical. the lt c2311 -16 has an onboard low drift ( 20ppm / c max) 2.048v or 4.096v temperature-compensated reference and provides an external 1.25v buffered reference input. the ltc2311-16 also has a high speed spi-compatible serial interface that supports cmos or lvds. the fast 5msps throughput with one-cycle latency makes the ltc2311-16 ideally suited for a wide variety of high speed applications. the ltc2311-16 dissipates only 50mw with a 5v supply and offers nap and sleep modes to reduce the power consumption to 5w for further power savings during inactive periods. 32k point fft f smpl = 5msps, f in = 2.2mhz applications n 5msps throughput rate n 3lsb inl (typ), 8lsb inl guaranteed n guaranteed 16-bit, no missing codes n 8v p-p differential inputs with wide input common mode range n 81db snr (typ) at f in = 2.2mhz n C90db thd (typ) at f in = 2.2mhz n guaranteed operation C40c to 125c n single 3.3v or 5v supply n low drift (20ppm/c max) 2.048v or 4.096v internal reference with 1.25v external reference input n 1.8v to 2.5v i/o voltages n cmos or lvds spi-compatible serial i/o n power dissipation 50mw at v dd = 5v (typ) n small 16-lead (4mm 5mm) msop package n high speed data acquisition systems n communications n remote data acquisition n imaging n optical networking n automotive n multiphase motor control l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. bipolar 25 25 47pf unipolar arbitrary differential inputs no configuration required in + , in ? differential ov dd v dd ltc2311-16 gnd 1.8v to 2.5v 231116 ta01a 1f 3.3v or 5v 0v 0v 0v 0v refin refout sdo a in ? a in + sck cnv cmos /lvds 1f lvds or cmos configurable i/o 10f 10f lt c2311-16 231116fa 1.5 2 2.5 ?140 ?120 ?100 ?80 ?60 ?40 ?20 snr = 81.6db 0 amplitude (dbfs) 231116 ta01b thd = ?90db sinad = 81.1db sfdr = 96db frequency (mhz) 0 0.5 1
2 for more information www.linear.com/ltc2311-16 pin configuration absolute maximum ratings supply voltage (v dd ) .................................................. 6v supply voltage (ov dd ) ................................................ 3v analog input voltage a in + , a in C (note 3) ................... C 0.3v to (v dd + 0.3v ) refin, refout ....................... C 0.3v to (v dd + 0.3v ) cnv (note 15) .......................... C 0.3v to (v dd + 0.3v ) digital input voltage (note 3) .......................... (gnd C 0.3v ) to (ov dd + 0.3v ) digital output voltage (note 3) .......................... (gnd C 0.3v ) to (ov dd + 0.3v ) power dissipation ............................................... 200mw operating temperature range lt c2311 c ................................................. 0 c to 70 c lt c2311 i .............................................. C 40 c to 85 c lt c2311 h .......................................... C 40 c to 125 c storage temperature range .................. C 65 c to 150 c (notes 1, 2) 1 2 3 4 5 6 7 8 gnd refin refout v dd gnd a in + a in ? gnd 16 15 14 13 12 11 10 9 17 gnd sck + sck ? sdo + sdo ? ov dd gnd cmos /lvds cnv top view mse package 16-lead (4mm 5mm) plastic msop t jmax = 150c, ja = 40c/w exposed pad (pin 17) is gnd, must be soldered to pcb lead free finish tape and reel part marking* package description temperature range ltc2311cmse-16#pbf ltc2311cmse-16#trpbf 231116 16-lead (4mm 5mm) plastic msop 0c to 70c ltc2311imse-16#pbf ltc2311imse-16#trpbf 231116 16-lead (4mm 5mm) plastic msop C40c to 85c ltc2311hmse-16#pbf ltc2311hmse-16#trpbf 231116 16-lead (4mm 5mm) plastic msop C40c to 125c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http: //www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http: //www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. order information http: //www.linear.com/product/ltc2311-16#orderinfo lt c2311-16 231116fa
3 for more information www.linear.com/ltc2311-16 electrical characteristics symbol parameter conditions min typ max units v in + absolute input range (a in + ) (note 5) l 0 v dd v v in C absolute input range (a in C ) (note 5) l 0 v dd v v in + C v in C input differential voltage range v in = v in + C v in C l Crefout refout v v cm common mode input range v cm = (v in + + v in C )/2 l 0 v dd v i in analog input dc leakage current l C1 1 a c in analog input capacitance 10 pf cmrr input common mode rejection ratio f in = 2.2mhz 85 db v ihcnv cnv high level input voltage l 1.3 v v ilcnv cnv low level input voltage l 0.5 v v incnv cnv input current v in = 0v to v dd l C 10 10 a the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 4). converter characteristics symbol parameter conditions min typ max units resolution l 16 bits no missing codes l 16 bits transition noise 1.7 lsb rms inl integral linearity error (note 6) l C8 3 8 lsb dnl differential linearity error l C0.99 0.4 0.99 lsb bze bipolar zero-scale error (note 7) l C12 0 12 lsb bipolar zero-scale error drift 0.01 lsb/c fse bipolar full-scale error v refout = 4.096v (refin grounded) (note 7) l C30 10 30 lsb bipolar full-scale error drift v refout = 4.096v (refin grounded) 15 ppm/c the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 4). lt c2311-16 231116fa
4 for more information www.linear.com/ltc2311-16 dynamic accuracy symbol parameter conditions min typ max units sinad signal-to-(noise + distortion) ratio f in = 2.2mhz, v refout = 4.096v, internal reference f in = 2.2mhz, v refout = 5v, external reference l 76 81 81.5 db db snr signal-to-noise ratio f in = 2.2mhz, v refout = 4.096v, internal reference f in = 2.2mhz, v refout = 5v, external reference l 76.5 81.6 82.3 db db thd total harmonic distortion f in = 2.2mhz, v refout = 4.096v, internal reference f in = 2.2mhz, v refout = 5v, external reference l C90 C88 C79 db db sfdr spurious free dynamic range f in = 2.2mhz, v refout = 4.096v, internal reference f in = 2.2mhz, v refout = 5v, external reference l 78 95 90 db db C3db input bandwidth 100 mhz aperture delay 500 ps aperture jitter 1 ps rms transient response full-scale step 3 ns the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c and a in = C1dbfs (notes 4, 8). internal reference characteristics symbol parameter conditions min typ max units v refout refout output voltage 4.75v < v dd < 5.25v 3.13v < v dd < 3.47v l l 4.082 2.042 4.096 2.048 4.110 2.054 v v refout input voltage 4.75v < v dd < 5.25v, refin = 0v (note 5) 3.13v < v dd < 3.47v, refin = 0v (note 5) l l 0.5 0.5 v dd v dd v v refout temperature coefficient (note 14) l 3 20 ppm/c refout short-circuit current v dd = 5.25v , forcing output to gnd l 30 ma refout line regulation v dd = 4.75v to 5.25v 0.3 mv/v refout load regulation i refout < 2ma 0.5 mv/ma refout input resistance (external reference mode) refin = 0v 60 k i refout refout input current (external reference mode) refin = 0v, refout = 4.096v (notes 9, 10) 700 a v refin refin output voltage 3.13v < v dd < 3.47v 4.75v < v dd < 5.25v l 1.245 1.25 1.255 v refin input voltage 3.13v < v dd < 3.47v (note 5) 4.75v < v dd < 5.25v (note 5) l l 1 1 1.85 1.45 v v refin short-circuit current v dd = 5.25v, forcing output to gnd l 250 a v il (v refin ) refin low level input voltage (external reference mode) 3.13v < v dd < 3.47v 4.75v < v dd < 5.25v l l 0.5 0.5 v v the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 4). lt c2311-16 231116fa
5 for more information www.linear.com/ltc2311-16 digital inputs and digital outputs symbol parameter conditions min typ max units cmos digital inputs and outputs v ih high level input voltage l 0.8 ? ov dd v v il low level input voltage l 0.2 ? ov dd v i in digital input current v in = 0v to ov dd l C10 10 a c in digital input capacitance 5 pf v oh high level output voltage i o = C500a l ov dd C 0.2 v v ol low level output voltage i o = 500a l 0.2 v i oz hi-z output leakage current v out = 0v to ov dd l C10 10 a i source output source current v out = 0v C10 ma i sink output sink current v out = ov dd 10 ma lvds digital inputs and outputs v id lvds differential input voltage 100 differential termination, ov dd = 2.5v l 240 600 mv v is lvds common mode input voltage 100 differential termination, ov dd = 2.5v l 1 1.45 v v od lvds differential output voltage 100 differential load, lvds mode, ov dd = 2.5v l 100 250 300 mv v os lvds common mode output voltage 100 differential load, lvds mode, ov dd = 2.5v l 0.85 1.2 1.4 v v od_lp low power lvds differential output voltage 100 differential load, low power, lvds mode, ov dd = 2.5v l 50 125 200 mv v os_lp low power lvds common mode output voltage 100 differential load, low power, lvds mode, ov dd = 2.5v l 0.9 1.2 1.4 v the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 4). lt c2311-16 231116fa
6 for more information www.linear.com/ltc2311-16 power requirements the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 4). adc timing characteristics symbol parameter conditions min typ max units cmos, lvds i/o modes f smpl maximum sampling frequency l 5 msps t cyc time between conversions (note 11) l 200 1000000 ns t acq acquisition time (note 11) l 28.5 ns t conv conversion time l 171.5 ns t cnvh cnv high time l 25 ns t dcnvsckl sck quiet time from cnv (note 11) l 9.5 ns t dscklcnvh sck delay time to cnv (note 11) l 19.1 ns t sck sck period (notes 12, 13) l 9.4 ns t sckh sck high time l 4 ns t sckl sck low time l 4 ns the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 4). symbol parameter conditions min typ max units v dd supply voltage 5v operation 3.3v operation l 4.75 3.13 5.25 3.47 v v ov dd supply voltage l 1.71 2.63 v i vdd supply current 5msps sample rate (a in + = a in C = 0v) l 9.5 12 ma i nap nap mode current conversion done (i vdd ) l 2.8 3.5 ma i sleep sleep mode current v dd = 3.3v, sleep mode (i vdd + i ovdd ) l 0.1 10 a cmos i/o mode i ovdd supply current 5msps sample rate (c l = 5pf) l 1.1 1.75 ma p d_3.3v power dissipation v dd = 3.3v 5msps sample rate (a in + = a in C = 0v) 30 mw nap mode v dd = 3.3v conversion done (i vdd + i ovdd ) 7.5 mw sleep mode v dd = 3.3v sleep mode (i vdd + i ovdd ) 0.3 w p d_5v power dissipation v dd = 5v 5msps sample rate (a in + = a in C = 0v) l 45 65 mw nap mode v dd = 5v conversion done (i vdd + i ovdd ) l 14 18 mw sleep mode v dd = 5v sleep mode (i vdd + i ovdd ) l 0.5 60 w lvds i/o mode i ovdd supply current 5msps sample rate (r l = 100) l 2.7 4.5 ma p d_3.3v power dissipation v dd = 3.3v 5msps sample rate (a in + = a in C = 0v) 36 mw nap mode v dd = 3.3v conversion done (i vdd + i ovdd ) 14 mw sleep mode v dd = 3.3v sleep mode (i vdd + i ovdd ) 0.3 w p d_5v power dissipation v dd = 5v 5msps sample rate (a in + = a in C = 0v) l 55 72 mw nap mode v dd = 5v conversion done (i vdd + i ovdd ) l 20 30 mw sleep mode v dd = 5v sleep mode (i vdd + i ovdd ) l 0.5 60 w lt c2311-16 231116fa
7 for more information www.linear.com/ltc2311-16 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground. note 3: when these pin voltages are taken below ground, or above v dd or ov dd , they will be clamped by internal diodes. this product can handle input currents up to 100ma below ground, or above v dd or ov dd , without latch-up. note 4: v dd = 5v, ov dd = 2.5v, refout = 4.096v, f smpl = 5mhz. note 5: recommended operating conditions. note 6: integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 7: bipolar zero error is the offset voltage measured from C0.5lsb when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111. full-scale bipolar error is the worst-case of Cfs or +fs untrimmed deviation from ideal first and last code transitions and includes the effect of offset error. note 8: all specifications in db are referred to a full-scale 4.096v input with refout = 4.096v. note 9: when refout is overdriven, the internal reference buffer must be turned off by setting refin = 0v. note 10: f smpl = 5mhz, i refout varies proportionally with sample rate. note 11: guaranteed by design, not subject to test. note 12: parameter tested and guaranteed at ov dd = 1.71v and ov dd = 2.5v. note 13: t sck of 9.4ns minimum allows a shift clock frequency up to 105mhz for falling edge capture. note 14: temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. note 15: cnv is driven from a low jitter digital source, typically at ov dd logic levels. this input pin has a ttl style input that will draw a small amount of current. figure 1. voltage levels for timing specifications 0.8 ? ov dd 0.2 ? ov dd 50% 50% 231116 f01 0.2 ? ov dd 0.8 ? ov dd 0.2 ? ov dd 0.8 ? ov dd t delay t width t delay adc timing characteristics symbol parameter conditions min typ max units t dscksdov sdo data valid delay from sck c l = 5pf (note 11) l 4 7.4 ns t hsdo sdo data remains valid delay from sck c l = 5pf (note 11) l 2 ns t dcnvsdov sdo data valid delay from cnv c l = 5pf (note 11) l 2.5 5 ns t dcnvsdoz bus relinquish time after cnv (note 11) l 5 ns t wake refout wake-up time c refout = 10f 10 ms the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c (note 4). lt c2311-16 231116fa
8 for more information www.linear.com/ltc2311-16 typical performance characteristics thd, harmonics vs input common mode (100khz to 2.2mhz) snr, sinad vs reference voltage, f in = 500khz 8k point fft, imd, f smpl = 5msps, a in + = 100khz, a in C = 2.2mhz 32k point fft, f smpl = 5msps, f in = 2.2mhz snr, sinad vs input frequency (100khz to 2.2mhz) thd, harmonics vs input frequency (100khz to 2.2mhz) integral nonlinearity vs output code differential nonlinearity vs output code dc histogram t a = 25c, v dd = 5v, ov dd = 2.5v, refout = 4.096v, f smpl = 5msps , unless otherwise noted. 231116 g09 frequency (mhz) amplitude (dbfs) 0 2.5 2 1 0.5 1.5 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 lt c2311-16 231116fa ?2 hd3 frequency (mhz) 0 0.5 1 1.5 2 2.5 ?110 ?105 ?1 ?100 ?95 ?90 ?85 thd, harmonics (dbfs) 231116 g06 thd hd2 hd3 input common mode (v) 0 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 ?110 1 ?105 ?100 ?95 ?90 ?85 ?80 thd, harmonics (dbfs) 231116 g07 snr sinad 2 v ref (v) 0.5 1 1.5 2 2.5 3 3.5 3 4 4.5 5 68 70 72 74 76 78 80 4 82 84 snr, sinad (dbfs) 231116 g08 inl error (lsb) 231116 g01 output code output code ?32768 ?16384 0 16384 32768 ?1 ?0.5 0 0.5 1 ?32768 dnl error (lsb) 231116 g02 = 1.7 output code ?5 ?4 ?3 ?2 ?1 0 ?16384 1 2 3 4 5 6 0 2000 4000 6000 0 8000 10000 12000 14000 16000 18000 20000 counts 231116 g03 snr = 81.6db 16384 thd = ?90db sinad = 81.1db sfdr = 96db frequency (mhz) 0 0.5 1 1.5 2 2.5 32768 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 amplitude (dbfs) 231116 g04 ?4 snr sinad frequency (mhz) 0 0.5 1 1.5 2 2.5 80.0 ?3 80.5 81.0 81.5 82.0 82.5 83.0 snr, sinad (dbfs) 231116 g05 thd hd2
9 for more information www.linear.com/ltc2311-16 typical performance characteristics refout output vs temperature i refout vs temperature, v ref = 4.096v refout output load regulation supply current vs sample frequency ov dd current vs sck frequency, c load = 10pf offset error vs temperature gain error vs temperature cmrr vs input frequency t a = 25c, v dd = 5v, ov dd = 2.5v, refout = 4.096v, f smpl = 5msps , unless otherwise noted. frequency (mhz) ?104 ?95 ?98 ?101 cmrr (db) ?92 ?89 ?83 ?86 ?80 231116 g12 0 1 0.5 1.5 2 2.5 lt c2311-16 231116fa 125 25 50 75 100 125 ?600 ?500 ?400 ?300 ?200 ?2.0 ?100 0 100 200 300 400 refout error (ppm, normalized to 25c) 231116 g13 sample frequency (msps) 0 ?1.5 1 2 3 4 5 5 6 7 8 8 ?1.0 9 10 supply current (ma) 231116 g16 ?0.5 0 0.5 1.0 1.5 2.0 temperature (c) offset error (lsb) 231116 g10 temperature (c) ?50 ?25 0 25 50 75 100 ?50 125 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 ?25 gain error (lsb) 231116 g11 temperature (c) ?50 ?25 0 25 50 75 100 0 125 696 698 700 702 704 706 708 reference current (a) 231116 g14 25 refout load current (ma) 0 0.5 1 1.5 2 4.0940 4.0945 4.0950 4.0955 50 4.0960 4.0965 4.0970 v ref (v) 231116 g15 sck frequency (mhz) 0 10 20 30 75 40 50 60 70 80 90 100 110 0 0.5 100 1.0 1.5 ov dd current (ma) 231116 g17 2.048v 4.096v temperature (c) ?50 ?25 0
10 for more information www.linear.com/ltc2311-16 pin functions gnd (pins 1, 5, 8, 11) : ground. these pins and the exposed pad (pin 17) must be tied directly to a solid ground plane. refin (pin 2) : reference buffer 1.25v input/output. an onboard buffer nominally outputs 1.25v to this pin. this pin should be decoupled closely to the pin (no vias) with a 10f (x5r, 0805 size) ceramic capacitor. the internal buffer driving this pin may be overdriven with an external reference. the refin pin, when pulled to gnd disables the refout pin buffer allowing an external reference to drive refout directly. refout (pin 3): reference buffer output. an onboard buffer nominally outputs 4.096v to this pin. this pin should be decoupled closely to the pin (no vias) with a 10f (x5r, 0805 size) ceramic capacitor. the internal buffer driving this pin may be disabled by grounding the refin pin. if the buffer is disabled, an external reference may drive this pin in the range of 1.25v to v dd . v dd (pin 4): power supply. bypass v dd to gnd with a 1f ceramic capacitor close to the v dd pin. a in + , a in C (pins 6, 7) : analog differential input pins. full- scale range (a in + to a in C ) is refout voltage. these pins can be driven from v dd to gnd. cnv (pin 9): convert input. this pin, when high, defines the sampling phase. when this pin is driven low, the con - version phase is initiated and output data is clocked out. this input pin is a ttl style input typically driven at ov dd levels with a low jitter pulse, but it is bound to v dd levels. this pin is unaffected by the cmos /lvds pin. cmos /lvds (pin 10): i/o mode select. ground this pin to enable cmos mode, tie to ov dd to enable lvds mode. float this pin to enable low power lvds mode. ov dd (pin 12): i/o interface digital power. the range of ov dd is 1.71v to 2.5v. this supply is nominally set to the same supply as the host interface (cmos : 1.8v or 2.5v, lvds : 2.5v). bypass ov dd to gnd with a 1f ceramic capacitor close to the ov dd pin. exposed pad (pin 17): ground. solder this pad to ground. cmos i/o mode sdo + (pin 14) : serial data output. the conversion result is shifted msb first on each falling edge of sck. the result is output on sdo + . the logic level is determined by ov dd . do not connect sdo C . sck + (pin 16) : serial data clock input. the falling edge of this clock shifts the conversion result msb first onto the sdo pins. drive sck + with a single-ended clock. the logic level is determined by ov dd . do not connect sck C . lvds i/o mode sdo + , sdo C (pins 14, 13) : serial data output. the con - version result is shifted msb first on each falling edge of sck. the result is output differentially on sdo + and sdo C . these pins must be differentially terminated by an external 100 resistor at the receiver (fpga). sck + , sck C (pins 16, 15) : serial data clock input. the falling edge of this clock shifts the conversion result msb first onto the sdo pins. drive sck + and sck C with a dif - ferential clock. these pins must be differentially terminated by an external 100 resistor at the receiver (adc). lt c2311-16 231116fa
11 for more information www.linear.com/ltc2311-16 functional block diagram cmos i/o mode lvds i/o mode 14 16-bit sar adc lvds/cmos tri-state serial output lvds/cmos receivers sdo + 12 10 ov dd 6 7 a in + 3 refout gnd 1, 5, 8, 11, 17 2 refin a in ? 16 sck + cmos/lvds timing control logic 231116 bda ? + s/h ldo 9 cnv v dd g 1.25v ref 4 14 13 16-bit sar adc lvds/cmos tri-state serial output lvds/cmos receivers sdo + sdo ? 12 10 ov dd 6 7 a in + 3 refout gnd 1, 5, 8, 11, 17 2 refin a in ? 16 15 sck + cmos/lvds sck ? timing control logic 231116 bdb ? + s/h ldo 9 cnv v dd g 1.25v ref 4 lt c2311-16 231116fa
12 for more information www.linear.com/ltc2311-16 timing diagram cmos, lvds i/o modes b15 b14 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b13 cnv sck sdo acquisition conversion and readout serial data bits b[15:0] correspond to previous conversion acquisition hi-z hi-z 231116 td lt c2311-16 231116fa
13 for more information www.linear.com/ltc2311-16 applications information overview the ltc2311-16 is a low noise, high speed 16-bit succes- sive approximation register (sar) adc with differential inputs and a wide input common mode range. operating from a single 3.3v or 5v supply, the ltc2311-16 has an 8v p-p differential input range, making it ideal for applica - tions which require a wide dynamic range. the lt c2311 -16 achieves 3lsb inl typical, no missing codes at 16 bits and 81db snr typical. the ltc2311-16 has an onboard reference buffer and low drift (20ppm/c max) 4.096v temperature-compensated reference. the ltc2311-16 also has a high speed spi- compatible serial interface that supports cmos or lvds. the fast 5msps throughput with one-cycle latency makes the ltc2311-16 ideally suited for a wide variety of high speed applications. the ltc2311 -16 dissipates only 50mw operating at a 5v supply. nap and sleep modes are also provided to reduce the power consumption of the ltc2311 - 16 during inactive periods for further power savings. converter operation the ltc2311-16 operates in two phases. during the acquisition phase, the sample capacitor is connected to the analog input pins a in + and a in C to sample the dif- ferential analog input voltage, as shown in figure 3. a falling edge on the cnv pin initiates a conversion. dur - ing the conversion phase, the 16-bit cdac is sequenced through a successive approximation algorithm for each input sck pulse, effectively comparing the sampled input with binary-weighted fractions of the reference voltage (e.g., v refout /2, v refout /4 v refout /65536) using a differential comparator. at the end of conversion, the cdac output approximates the sampled analog input. the adc control logic then prepares the 16-bit digital output code for serial transfer. transfer function the ltc2311-16 digitizes the full-scale voltage of 2 refout into 2 16 levels, resulting in an lsb size of 125v with refout = 4.096v. the ideal transfer function is shown in figure 2. the output data is in 2 s comple - ment format. analog input the differential inputs of the ltc2311-16 provide great flexibility to convert a wide variety of analog signals with no configuration required. the ltc2311-16 digitizes the difference voltage between the a in + and a in C pins while supporting a wide common mode input range. the analog input signals can have an arbitrary relationship to each other, provided that they remain between v dd and gnd. the ltc2311 -16 can also digitize more limited classes of analog input signals such as pseudo-differential unipolar/ bipolar and fully differential with no configuration required. the analog inputs of the ltc2311-16 can be modeled by the equivalent circuit shown in figure 3. the back-to- back diodes at the inputs form clamps that provide esd protection. in the acquisition phase, 10pf (c in ) from the figure 2. ltc2311 -16 transfer function figure 3. the equivalent circuit for the differential analog input of the ltc2311-16 input voltage (v) ?fsr/2 +fsr/2 ? 1lsb output code (two?s complement) 231116 f02 011...111 011...110 111...111 100...000 100...001 000...000 000...001 ?1 lsb fsr = +fs ? ?fs 1lsb = fsr/65535 0 1 lsb r on 15 r on 15 bias voltage 231116 f03 c in 10pf v dd c in 10pf v dd a in ? a in + lt c2311-16 231116fa
14 for more information www.linear.com/ltc2311-16 applications information sampling capacitor in series with approximately 15 (r on ) from the on-resistance of the sampling switch is connected to the input. any unwanted signal that is com - mon to both inputs will be reduced by the common mode rejection of the adc sampler. the inputs of the adc core draw a small current spike while charging the c in capaci - tors during acquisition. single-ended signals single-ended signals can be directly digitized by the ltc2311-16. these signals should be sensed pseudo- differentially for improved common mode rejection. by connecting the reference signal (e.g., ground sense) of the main analog signal to the other a in pin, any noise or disturbance common to the two signals will be rejected by the high cmrr of the adc. the ltc2311-16 flexibility handles both pseudo-differential unipolar and bipolar sig- nals, with no configuration required. the wide common mode input range relaxes the accuracy requirements of any signal conditioning circuits prior to the analog inputs. pseudo-differential bipolar input range the pseudo-differential bipolar configuration represents driving one of the analog inputs at a fixed voltage, typically v ref /2, and applying a signal to the other a in pin. in this case the analog input swings symmetrically around the fixed input yielding bipolar two s complement output codes with an adc span of half of full-scale. this configuration is illustrated in figure 4, and the corresponding transfer function in figure 5. the fixed analog input pin need not be set at v ref /2, but at some point within the v dd rails allowing the alternate input to swing symmetrically around this voltage. if the input signal (a in + C a in C ) swings beyond refout/2, valid codes will be generated by the adc and must be clamped by the user, if necessary. figure 4. pseudo-differential bipolar application circuit figure 5. pseudo-differential bipolar transfer function 25 25 47pf v ref 0v v ref 0v v ref /2 v ref /2 v ref 10k 10k + ? + ? ltc2311-16 lt1819 231116 f04 sdo refin refout sck a in ? a in + cnv to control logic (fpga, cpld, dsp, etc.) 10f 10f 1f 231116 f05 ?v ref ?16385 16384 ?32768 32767 v ref dotted regions available but unused a in (a in + ? a in ? ) adc code (2?s complement) ?v ref /2 v ref /2 0 lt c2311-16 231116fa
15 for more information www.linear.com/ltc2311-16 applications information pseudo-differential unipolar input range the pseudo-differential unipolar configuration represents driving one of the analog inputs at ground and applying a signal to the other a in pin. in this case, the analog input swings between ground and v ref yielding unipolar two s complement output codes with an adc span of half of full-scale. this configuration is illustrated in figure 6, and the corresponding transfer function in figure 7. if the input signal (a in + C a in C ) swings negative, valid codes will be generated by the adc and must be clamped by the user, if necessary. figure 6. pseudo-differential unipolar application circuit figure 7. pseudo-differential unipolar transfer function 25 25 47pf v ref 0v v ref 0v + ? ltc2311-16 lt1818 231116 f06 sdo refin refout sck a in ? a in + cnv to control logic (fpga, cpld, dsp, etc.) 10f 10f 231116 f07 ?v ref ?16385 16384 ?32768 32767 v ref dotted regions available but unused a in (a in + ? a in ? ) adc code (2?s complement) ?v ref /2 v ref /2 0 lt c2311-16 231116fa
16 for more information www.linear.com/ltc2311-16 applications information single-ended-to-differential conversion while single-ended signals can be directly digitized as pre - viously discussed, single-ended to differential conversion circuits may also be used when higher dynamic range is desired. by producing a differential signal at the inputs of the ltc2311-16, the signal swing presented to the adc is maximized, thus increasing the achievable snr. the lt ? 1819 high speed dual operational amplifier is recommended for performing single-ended-to-differential conversions, as shown in figure 8. in this case, the first amplifier is configured as a unity-gain buffer and the single-ended input signal directly drives the high imped - ance input of this amplifier. fully-differential inputs to achieve the full distortion performance of the lt c2311 -16, a low distortion fully-differential signal source driven through the lt1819 configured as two unity-gain buffers, as shown in figure 9, can be used. this circuit achieves a thd specification of C85db at input frequencies of 500khz and less. data sheet typical performance curves are taken using a harmonic rejection filter between the adc and the signal source to eliminate the op amp as the dominant source of distortion. the fully-differential configuration yields an analog input span (a in + C a in C ) of refout. in this configuration, the input signal is driven on each a in pin, typically at equal spans but opposite polarity. this yields a high common mode rejection on the input signals. the common mode voltage of the analog input can be anywhere within the v dd input range, but will be limited by the peak swing of the full-range input signal. for example, if the internal refer - ence is used with v dd = 5v dc , the full-range input span will be 4.096v. half of the input span is typically driven on each a in pin, yielding a signal span for each a in pin of 4.096v p-p . this leaves ~0.9v of common mode variation tolerance. when using external references, it is possible to increase common mode tolerance by compressing the adc full-range codes into a tighter range. for example, using an external 2.048v reference with v dd = 5v the total span would be 2.048v and each a in span would be lim- ited to 2.048v p-p allowing a common mode range of ~3v. compressing the input span would incur a snr penalty of approximately 2db. input span compression may be useful if single-supply analog input drivers are used which figure 8. single-ended to differential driver figure 9. lt1819 buffering a fully-differential signal source v ref 0v v ref 0v v ref 0v v ref /2 + ? + ? 200 200 lt1819 231116 f08 v ref 0v v ref 0v v ref 0v v ref 0v + ? + ? lt1819 231116 f09 lt c2311-16 231116fa
17 for more information www.linear.com/ltc2311-16 applications information cannot swing rail-to-rail. the fully-differential configuration is illustrated in figure 10, with the corresponding transfer function illustrated in figure 11. input drive circuits a low impedance source can directly drive the high im - pedance inputs of the ltc2311 -16 without gain error. a high impedance source should be buffered to minimize settling time during acquisition and to optimize the dis - tortion performance of the adc. minimizing settling time is important even for dc inputs, because the adc inputs draw a current spike at the start of the acquisition phase. for best performance, a buffer amplifier should be used to drive the analog inputs of the ltc2311-16. the amplifier provides low output impedance to minimize gain error and allow for fast settling of the analog signal during the acquisition phase. it also provides isolation between the signal source and the adc inputs, which draw a small current spike during acquisition. figure 10. fully-differential application circuit figure 11. fully-differential transfer function 25 25 47pf v ref 0v v ref 0v v ref 0v v ref 0v + ? + ? ltc2311-16 l t 1 8 1 9 231116 f10 sdo refin refout sck a in ? a in + cnv to control logic (fpga, cpld, dsp, etc.) 10f 10f 231116 f11 ?v ref ?16385 16384 ?32768 32767 v ref a in (a in + ? a in ? ) adc code (2?s complement) ?v ref /2 v ref /2 0 lt c2311-16 231116fa
18 for more information www.linear.com/ltc2311-16 applications information input filtering the noise and distortion of the buffer amplifier and signal source must be considered since they add to the adc noise and distortion. noisy input signals should be filtered prior to the buffer amplifier input with a low bandwidth filter to minimize noise. the simple 1-pole rc lowpass filter shown in figure 12 is sufficient for many applications. 10f capacitor should be soldered as close as possible to the refout pin to minimize wiring inductance. the refin pin produces a 1.25v precision reference which should also be bypassed with a 10f (x5r, 0805 size) ceramic capacitor. the refin pin may be overdriven with an external precision reference as shown in figure 13a. figure 12. input signal chain 50 single-ended input signal 231116 f12 bw = 1mhz 3.3nf single-ended to differential driver in + in ? ltc2311 the input resistor divider network, sampling switch on- resistance (r on ) and the sample capacitor (c in ) form a second lowpass filter that limits the input bandwidth to the adc core to 110mhz. a buffer amplifier with a low noise density must be selected to minimize the degradation of the snr over this bandwidth. high quality capacitors and resistors should be used in the rc filters since these components can add distortion. npo and silver mica type dielectric capacitors have excellent linearity. carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. metal film surface mount resistors are much less susceptible to both problems. adc reference internal reference the ltc2311-16 has an on-chip, low noise, low drift (20ppm/c max), temperature compensated bandgap ref - erence that is internally buffered and is available at refin (pin 2). the internal reference buffer gains the refin pin voltage (1.25v) to refout (pin 3) and is 4.096v for a 5v supply and 2.048v for 3.3v supply. bypass refout to gnd with a 10f (x5r, 0805 size) ceramic capacitor. the figure 13a. ltc2311 -16 with an external refin voltage v in shdn v out_f v out_s ltc6655-1.25v ltc2311-16 gnd 231116 f13a 5v to 13.2v refout refin 0.1f 10f 10f table 1. internal reference with internal buffer v dd refin refout fully differential input range unipolar input range bipolar input range 5v 1.25v 4.096v 4.096v 0v to 4.096v 2.048v 3.3v 1.25v 2.048v 2.048v 0v to 2.048v 1.024v table 2. external reference with internal buffer v dd refin (over- driven) refout fully differential input range unipolar input range bipolar input range 5v 1v 3.3v 3.3v 0v to 3.3v 1.65v 1.25v 4.096v 4.096v 0v to 4.096v 2.048v 1.45v 4.7v 4.7v 0v to 4.7v 2.35v 3.3v 1v 1.65v 1.65v 0v to 1.65v 0.825v 1.25v 2.048v 2.048v 0v to 2.048v 1.024v 1.85 3v 3v 0v to 3v 1.5v table 3. external reference unbuffered v dd refin refout fully differential input range unipolar input range bipolar input range 5v 0v 0.5v 0.5v 0v to 0.5v 0.25v 0v 5v 5v 0v to 5v 2.5v 3.3v 0v 0.5v 0.5v 0v to 0.5v 0.25v 0v 3.3v 3.3v 0v to 3.3v 1.65v lt c2311-16 231116fa
19 for more information www.linear.com/ltc2311-16 applications information external reference the internal reference buffer can also be overdriven from 1.25v to 5v with an external reference at refout as shown in figure 13b. in this configuration, refin must be grounded to disable the internal reference buffer. a 55k internal resistance loads the refout pin when the reference buffer is disabled. to maximize the input signal swing and corresponding snr, the ltc6655-5 is recommended when overdriving refout. the ltc6655 -5 offers the same small size, accuracy, drift and extended temperature range as the ltc6655-4.096. by using a 5v reference, a higher snr can be achieved. we recommend bypassing the ltc6655-5 with a 10f ceramic capacitor (x5r, 0805 size) as close as possible to the refout pin. will affect the accuracy of the output code. due to the one-cycle conversion latency, the first conversion result at the beginning of a burst sampling period will be invalid. if an external reference is used to buffer/drive the refout pin, the fast settling ltc6655 reference is recommended. figure 13b. ltc2311 -16 with an external refout voltage v in shdn v out_f v out_s ltc6655-4.096 ltc2311-16 gnd 231116 f13b 5v to 13.2v refout refin 0.1f 10f internal reference buffer transient response the refout pin of the ltc2311 -16 draws charge (q conv ) from the external bypass capacitors during each conver - sion cycle. if the internal reference buffer is overdriven, the external reference must provide all of this charge with a dc current equivalent to i refout = q conv /t cyc . thus, the dc current draw of refout depends on the sampling rate and output code. in applications where a burst of samples is taken after idling for long periods, as shown in figure 14 , i refout quickly goes from approximately ~75a to a maximum of 700a for refout = 5v at 5msps. this step in dc current draw triggers a transient response in the external reference that must be considered since any deviation in the voltage at refout figure 14. cnv waveform showing burst sampling figure 15. transient response of the ltc2311-16 cnv 231116 f14 idle period 231116 f15 time (ns) output code 0 200 100 35000 30000 25000 20000 15000 10000 5000 0 ?5000 dynamic performance fast fourier transform (fft) techniques are used to test the adcs frequency response, distortion and noise at the rated throughput. by applying a low distortion sine wave and analyzing the digital output using an fft algorithm, the adcs spectral content can be examined for frequen - cies outside the fundamental. the ltc2311-16 provides guaranteed tested limits for both ac distortion and noise measurements. signal-to-noise and distortion ratio (sinad) the signal-to-noise and distortion ratio (sinad) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components at the a/d output. the output is bandlimited to frequencies from above dc and below half the sampling lt c2311-16 231116fa
20 for more information www.linear.com/ltc2311-16 applications information frequency. figure 16 shows that the ltc2311-16 achieves a typical sinad of 81db at a 5mhz sampling rate with a 2.2mhz input. power considerations the ltc2311 -16 requires two power supplies: the 5v power supply (v dd ), and the digital input/output interface power supply (ov dd ). the flexible ov dd supply allows the ltc2311-16 to communicate with any digital logic operating between 1.8v and 2.5v . when using lvds i/o, the ov dd supply must be set to 2.5v. power supply sequencing the ltc2311-16 does not have any specific power sup - ply sequencing requirements. care should be taken to adhere to the maximum voltage relationships described in the absolute maximum ratings section. the ltc2311- 16 has a power-on-reset (por) circuit that will reset the ltc2311 -16 at initial power-up or whenever the power supply voltage drops below 2v. once the supply voltage re-enters the nominal supply voltage range, the por will reinitialize the adc. no conversions should be initiated until 10ms after a por event to ensure the reinitialization period has ended. any conversions initiated before this time will produce invalid results. figure 16. 32k point fft of the ltc2311-16 figure 17. power supply current of the ltc2311-16 versus sampling rate signal-to-noise ratio (snr) the signal-to-noise ratio (snr) is the ratio between the rms amplitude of the fundamental input frequency and the rms amplitude of all other frequency components except the first five harmonics and dc. figure 16 shows that the ltc2311-16 achieves a typical snr of greater than 81db at a 5mhz sampling rate with a 2.2mhz input. total harmonic distortion (thd) total harmonic distortion (thd) is the ratio of the rms sum of all harmonics of the input signal to the fundamental itself. the out-of-band harmonics alias into the frequency band between dc and half the sampling frequency (f smpl /2). thd is expressed as: thd = 20log v2 2 + v3 2 + v4 2 ++ vn 2 v1 where v1 is the rms amplitude of the fundamental frequency and v2 through vn are the amplitudes of the second through nth harmonics. the thd specifications for the ltc2311 -16 consider the first seven harmonics (i.e. n=7). figure 16 shows that the ltc2311-16 achieves a typical thd of C90db at a 5mhz sampling rate with a 2.2mhz input. lt c2311-16 231116fa 1.5 2 2.5 ?140 ?120 ?100 ?80 ?60 ?40 ?20 snr = 81.6db 0 amplitude (dbfs) 231116 f16 sample frequency (msps) 0 1 2 3 4 5 thd = ?90db 5 6 7 8 8 9 10 supply current (ma) 231116 g16 sinad = 81.1db sfdr = 96db frequency (mhz) 0 0.5 1
21 for more information www.linear.com/ltc2311-16 applications information timing and control cnv timing the ltc2311-16 sampling and conversion is controlled by cnv . a rising edge on cnv will start sampling and the falling edge starts the conversion and readout process. the conversion process is timed by the sck input clock. for optimum performance, cnv should be driven by a clean low jitter signal. the typical application at the back of the data sheet illustrates a recommended implementation to reduce the relatively large jitter from an fpga cnv pulse source. note the low jitter input clock times the falling edge of the cnv signal. the rising edge jitter of cnv is much less critical to performance. the typical pulse width of the cnv signal is 30ns at a 5msps conversion rate. sck serial data clock input the falling edge of this clock shifts the conversion result msb first onto the sdo pins. a 105mhz external clock must be applied at the sck pin to achieve 5msps throughput. nap/sleep modes nap mode is a method to save power without sacrificing power-up delays for subsequent conversions. sleep mode has substantial power savings, but a power-up delay is incurred to allow the reference and power systems to become valid. to enter nap mode on the ltc2311-16, the sck signal must be held high or low and a series of two cnv pulses must be applied. this is the case for both cmos and lvds modes. the second rising edge of cnv initiates the nap state. the nap state will persist until either a single rising edge of sck is applied, or further cnv pulses are applied. the sck rising edge will put the ltc2311-16 back into the operational (full-power) state. when in nap mode, two additional pulses will put the ltc2311-16 in sleep mode. when configured for cmos i/o operation, a single rising edge of sck can return the ltc2311 -16 into operational mode. a 10ms delay is necessary after exiting sleep mode to allow the reference buffer to recharge the external filter capacitor. in lvds mode, exit sleep mode by supplying a fifth cnv pulse. the fifth pulse will return the ltc2311 -16 to operational mode, and further sck pulses will keep the part from re-entering nap and sleep modes. the fifth sck pulse also works in cmos mode as a method to exit sleep. in the absence of sck pulses, repetitive cnv pulses will cycle the ltc2311-16 between operational, nap and sleep modes indefinitely. refer to the timing diagrams in figure 18, figure 19, figure 20 and figure 21 for more detailed timing information about sleep and nap modes. figure 18. cmos and lvds mode nap and wake using sck full power mode 1 2 cnv sck hold static high or low nap mode sdo wake on 1st sck edge z z 231116 f18 lt c2311-16 231116fa
22 for more information www.linear.com/ltc2311-16 applications information figure 19. cmos mode sleep and wake using sck figure 20. lvds and cmos mode sleep and wake using cnv figure 21. ltc2311 -16 timing diagram, cmos, lvds i/o modes full power mode 1 2 3 4 4.096v 4.096v refout recovery refout cnv sck hold static high or low nap mode sleep mode sdo wake on 1st sck edge z z z z 231116 f19 t wake 1 2 3 4 5 4.096v 4.096v refout recovery refout cnv sck hold static high or low nap mode sleep mode full power mode sdo wake on 5th csb edge z z z z z 231116 f20 t wake b15 b14 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 b13 t conv t acq serial data bits b[15:0] correspond to previous conversion cnv sck sdo 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 t cnvh hi-z hi-z t cyc 231116 f21 t dscklcnvh t dcnvsdoz t sck t sckl t sckh t hsdo t dscksdov t dcnvsckl t dcnvsdov lt c2311-16 231116fa
23 for more information www.linear.com/ltc2311-16 digital interface the ltc2311 -16 features a serial digital interface that is simple and straightforward to use. the flexible ov dd supply allows the ltc2311-16 to communicate with any digital logic operating between 1.8v and 2.5v. a 105mhz external clock must be applied at the sck pin to achieve 5msps throughput. in addition to a standard cmos spi interface, the ltc2311 - 16 provides an optional lvds spi interface to support low noise digital design. the cmos /lvds pin is used to select the digital interface mode. the falling edge of sck outputs the conversion result msb first on the sdo pins. in cmos mode, use the sdo + pin as the serial data output and the sck + pin as the serial clock input. do not connect the sdo C and sck C pins as they have internal pull-downs to gnd. in lvds mode, use the sdo + /sdo C pins as a differential output. these pins must be differentially terminated by an external 100 resistor at the receiver (fpga). the sck + / sck C pins are a differential input and must be terminated differentially by an external 100 resistor at the receiver (adc), see figure 22. board layout to obtain the best performance from the ltc2311-16, a four layer printed circuit board is recommended. layout for the printed circuit board (pcb) should ensure the digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital clocks or signals adjacent to analog signals or underneath the adc. a single solid ground plane is used. bypass capacitors to the supplies are placed as close as possible to the supply pins. low impedance common returns for these bypass capacitors are essential to the low noise operation of the adc. the analog input traces are screened by ground. reference design for a detailed look at the reference design for this converter, including schematics and pcb layout, please refer to the dc2425, the evaluation kit for the ltc2311-16. applications information figure 22. ltc2311 -16 using the lvds interface 2.5v 2.5v ov dd ltc2311-16 fpga or dsp 231116 f22 sck + sck ? sdo + sdo ? cnv cmos /lvds + ? 100 + ? 100 lt c2311-16 231116fa
24 for more information www.linear.com/ltc2311-16 package description please refer to http: //www.linear.com/product/ltc2311-16#packaging for the most recent package drawings. msop (mse16) 0213 rev f 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16 16151413121110 1 2 3 4 5 6 7 8 9 9 1 8 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.10 (.201) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref mse package 16-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1667 rev f) lt c2311-16 231116fa
25 for more information www.linear.com/ltc2311-16 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 07/16 updated the max value for refout short-circuit current removed power consumption max values changed the note for t dscksdov 4 6 7 lt c2311-16 231116fa
26 for more information www.linear.com/ltc2311-16 ? linear technology corporation 2016 lt 0716 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc2311-16 related parts typical application part number description comments adcs ltc2323-16/ltc2323-14/ ltc2323-12 16-/14-/12-bit, 5msps, simultaneous sampling dual adcs 3.3v/5v supply, 40mw/ch, 20ppm/c max internal reference, flexible inputs, 4mm 5mm qfn-28 package ltc1407/ltc1407-1 12-/14-bit, 3msps simultaneous sampling adc 3v supply, 2-channel differential, 1.5msps per channel throughput, unipolar/bipolar inputs, 14mw, msop package ltc2314-14 14-bit, 4.5msps serial adc 3v/5v supply, 18mw/31mw, 20ppm/c max internal reference, unipolar inputs, 8- lead tsot-23 package ltc2321-16/ltc2321-14/ LTC2321-12 16-/14-/12-bit, 2msps, simultaneous sampling dual adcs 3.3v/5v supply, 33mw/ch, 10ppmc max internal reference, flexible inputs, 4mm 5mm qfn-28 package ltc2370-16/ltc2368-16/ ltc2367-16/ltc2364 -16 16-bit, 2msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, pseudo-differential unipolar input, 94db snr, 5v input range, dgc, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages ltc2380-16/ltc2378-16/ ltc2377-16/ltc2376-16 16-bit, 2msps/1msps/500ksps/250ksps serial, low power adc 2.5v supply, differential input, 96.2db snr, 5v input range, dgc, pin-compatible family in msop-16 and 4mm 3mm dfn-16 packages dacs ltc2632 dual 12-/10-/8-bit, spi v out dacs with internal reference 2.7v to 5.5v supply range, 10ppm/c reference, external ref mode, rail-to-rail output, 8-pin thinsot ? package ltc2602/ltc2612/ ltc2622 dual 16-/14-/12-bit spi v out dacs with external reference 300a per dac, 2.5v to 5.5v supply range, rail-to-rail output, 8-lead msop package references ltc6655 precision low drift, low noise buffered reference 5v/4.096v/3.3v/3v /2.5v/2.048v/1.25v, 2ppm/c, 0.25ppm peak-to-peak noise, msop-8 package ltc6652 precision low drift, low power buffered reference 5v/4.096v/3.3v/3v/2.5v/2.048v/1.25v, 5ppm/c, 2.1ppm peak-to-peak noise, msop-8 package amplifiers lt1818/lt1819 400mhz, 2500v/s, 9ma single/dual operational amplifiers C85dbc distortion at 5mhz, 6nv/hz input noise voltage, 9ma supply current, unity-gain stable lt1806 325mhz, single, rail-to-rail input and output, low distortion, low noise precision op amps C80dbc distortion at 5mhz, 3.5nv/hz input noise voltage, 9ma supply current, unity-gain stable lt6200 165mhz, rail-to-rail input and output, 0.95nv/hz low noise, op amp family low noise, low distortion, unity-gain stable low jitter clock timing with rf sine generator using clock squaring/level-shifting circuit and retiming flip-flop 50 nc7svuo4p5x nc7svuo4p5x conv enable master_clock conv 1k 1k ltc2311-16 231116 ta02 sck gnd clr nc7sv74kbx control logic (fpga, cpld, dsp, etc.) pre cnv cmos /lvds v cc v cc q d sdo 0.1f 10 lt c2311-16 231116fa

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